[GSoC Weekly Overview]: Change of Plan

Big news of the week is: I have changed to Plan B implementation for capturing VGA. This change was forced due to narrowing road in the first implementation. The final nail in coffin was when even Xilinx’s AD9984A code (from UG458) gave the exact same result as my code. Gah! So, I decided enough is enough, lets move to plan B. And the results do look promising!

What’s exactly is Plan B?

In this implementation, I’m using a 24-bit wide and 4096 dept FIFO with independent read and write clocks.
Why independent clocks? Thats because the DATACK and the img_pclk are different, even though supposedly at same frequency, but they drift over time. So, I’ll be pushing data into the FIFO first using DATACK, then after slight delay, I’ll start reading it using the accurate clock img_pclk (which would be driving the whole HDMI encoder). The problem of FIFO overflow and underflow is eliminated by a simple realization that out of the complete line-scan period (1344) only 1024 cycles are the active ones. That means, I can use rest of the cycles to synchronize and reset the FIFO at the appropriate time.
I have done the simulations and just at the time of this writing, ran it on Atlys! And lo! The flickerings are gone!! The image looks perfect from a distance, but when I go near, I see the pixels shaking by 1 (or max 2) pixels. I think I can correct this using a 2-FIFO pipeline, where 1 one written and the other one is read.
I’m pretty much happy with the result of 4 days of coding and simulation.


Unfortunately, due to my priority to VGA Capturing (due to less and less time remaining), the target for at least a partially routable PCB was not achieved. But, the schematic is pretty much up for review. After some changes if required, I will finalize it and move to PCB routing.
Also, this week I bought my first ever Hot-Air Soldering Machine for soldering the AD9984A and other ICs to the second prototype of PCBv01. The prototype has been partially soldered. Parts remaining to be soldered are AD3334 voltage reg, Ferrite Beads and Resistor Network. I’m awaiting their delivery from Element14.

In all, I’m happy with this week. Very good progress in the capturing and some in PCB area.

Upcoming Week:

This week my goal will be to finalize the PCB and and get the VGA capture rock solid. And, I’m confident [yeah, confidence returned after 3 weeks of almost continuous failures! :) B-) ] that I’ll complete this goal. The PCB might get delayed by 1-2 days max. After that, my focus in remaining weeks would be PCBv02 testing (after receiving from fab), HDMI2USB integration (which is going to give some headache, so I’m taking some buffer time for that). Minor issues like, I2C and autodetection features are 1 or 2 day jobs max.

So, after much delay due to capturing (&timing?) headache, the project is back on track!! Feels awesome!

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