[GSoC Daily Log]: Reading

Wednesday, 2nd July:

  • Read the about clock-crossing. Some implementation assume data arriving a slower rate compared to both clocks. While some other use FIFOs. 
  • Read the Xilinx’s app-note XAPP224 - Data Recovery. Seems this one can be used. Only problem is that it specifies “ At least one data transition is required in the time that the circuit takes to drift one-quarter clock period. Example for a local oscillator 401 MHz and data arriving a 400Mbps, the circuit requires at least one negative transition every 100 clock cycles to function correctly.” Also it says “Care should be taken if the received data is a raw bitstream, because an adequate number of transitions may not exist.”
  • Started writing a new improved test code

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