[GSoC Daily Log]: Interesting

Monday, 7th July 2014:

  • Some amusing things going on! If I use DCM_SP in place of DCM_CLKGEN, with *exact* same CLKFX_DIVIDE & CLKFX_MULTIPLY values and also same connections, the screen would go blank, but the PLL would indicate locked status. Same goes for the case when I directly connect the PLL to DATACK instead of through DCM.
    I suspect this tells that the DATACK clock is not clean.
  • I strongly suspected, that this may be due to design issue. So, I investigated some documents on DATACK. First, the AD9984A’s datasheet. It’s PCB design guidelines say adding 50-200 ohm resistor to reduce reflections. But, The reference schematic for AD9984 uses 22 ohm resistors for all clocks (DATACK, HSOUT, VSOUT & SOGOUT) whereas, uses 50 ohm for the data lines. I found one more schematic(FMCVideo_sch_RevD.pdf)  from Xilinx using AD9984A. This one didn’t use any series resistor on any digital lines. I don’t know how much impact it does at 65MHz, but I strongly suspect either this or other physical design issue in the PCB.

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