[GSoC Daily Log]: Trails & errors - Part 2

Saturday, 21st June 2014:

  • Tried many different options ofr reducing flickering including porting the code from here https://github.com/desaster/grabor. Result: Unsuccessful in removing flickering. Same result as before
  • Tried many other hit and trials, all others also resulted in same or worse result. No better result.
  • Finally, fed up after much blind trials, decided on getting a good debug setup.
  • Tried Ajith’s UART code for Atlys. From here. Worked successfully on standalone project.
  • Added the previous UART code to the project. Clocks had to be modified and core-gen removed.
  • Successfully getting UART debug output from the project. Few Observations:
    • At the end of frame, CounterY should be 805 ideally. It fluctuates b/w 805 and 806 with mostly at 806.
    • At the end of frame, CounterX should be 1343 ideally. From the debug output, it fluctuates b/w 1341, 1342 & 1343 (sometimes 0 too :o !)
    • From the AD9984A I2C Status registers, the actual number of HSYNCs per VSYNC reported by AD9984A is 806 which is ideal and correct.
    • Pixel Clock is unstable in that, direct generation of a sample pattern using it also results in slightly flickering output.

Posted in , . Bookmark the permalink. RSS feed for this post.

Leave a Reply


Swedish Greys - a WordPress theme from Nordic Themepark. Converted by LiteThemes.com.