[GSoC Daily Log]: Drivers and PLL

Wednesday, 25th June 2014:

  • Okay, so the cdc_acm driver mentioned in the previous snippet was only reading the data. Was unable to transmit them
  • Tried once again the Vizzini driver. Worked this time (both transmit and receive). Using Ajith’ sample code.
  • Tried to stabilize HSYNC and VSYNC counter values by enabling VSYNC Filter and PLL Filter(reg 0x20 Bit 2 and reg 0x14 Bit 2, here, Green highlighted are the changes)  inside the AD9984A, some observations:
    • It was able to stabilize CounterY at the end of frame to perfect 806 value.
    • It was able to stabilize CounterX value the at end of horizontal line scan to perfect 1343 value.
    • It was unable to stabilize CounterX value at the end of frame. Values vary quite much still.

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